The present invention relates generally to integrated circuit testing, and, more particularly, to a system and method for integrated circuit (IC) device testing assisted by scan.
Typically, in the past, integrated circuit (IC) devices have been tested and verified using a combination of test methods. For example, IC devices were originally tested and verified to be defect free using functional test vectors, which stimulate and verify the device functionality at the pin level only. While this approach provides relatively short test times, it is typically ineffective for detecting faults deep within today""s large and complex IC devices.
As a way of augmenting functional test vector analysis, scan testing of IC devices was introduced. Scan testing allows access to the internal registers of an IC device, providing much higher fault coverage than that attainable by functional test vector testing. However, scan testing greatly extends test time.
Still another improvement was attained by the advent of built in self testing (BIST), which provides lower test times than scan testing and provides higher test coverage than traditional pin based functional vector testing. Unfortunately, BIST testing typically results in less than 90% fault coverage, which is insufficient to test today""s large IC devices.
Another drawback with BIST testing is that BIST specific hardware must be designed into the IC device. Typically, this includes a signature analysis register, which compares the resultant test data against the expected test result. Additionally, a linear feedback shift register (LFSR) is required to provide a fixed sequence of stimulus to the logic under test. The LFSR typically must be designed and redesigned to obtain 85-90% fault coverage. In complex designs, BIST circuitry is typically required for each major functional block of the IC device, thus further increasing the design cycle time and consuming valuable space on the device for the test logic.
Unfortunately, because the BIST testing is hardware specific, it may not be modified to enhance deficiencies in test coverage once the design of the IC device is complete.
Therefore, it would be desirable to improve test coverage of an IC device while minimizing test times, while being able to modify the test logic after the design of the IC device is complete.
The invention provides a system and method for testing in an integrated circuit.
In architecture, the present invention may be conceptualized as a system for testing an integrated circuit, the integrated circuit including core logic, the system comprising: a boundary scan ring, the boundary scan ring including a plurality of registers; a functional scan ring within the integrated circuit, the functional scan ring including a plurality of registers, the functional scan ring coupled to the boundary scan ring; multiplexer logic configured to control the boundary scan ring such that the boundary scan ring recirculates data within the boundary scan registers; and clock logic configured to shift the boundary scan registers with a clock signal while the functional scan registers capture data supplied by the boundary scan ring, and the boundary scan registers capture data from the functional scan registers.
The present invention may also be conceptualized as a method for testing an integrated circuit, the integrated circuit including core logic and a plurality of functional scan registers coupled to a plurality of boundary scan registers, the method comprising the steps of: establishing a plurality of test vectors; initializing the functional scan registers and the boundary scan registers; clocking the integrated circuit; supplying data input signals from the boundary scan registers to the functional scan registers; receiving in the boundary scan registers data output signals from the functional scan registers; and outputting the data output signals and comparing the data output signals to the test vectors in order to determine whether the data output signals are an accurate representation of the test vectors.
The invention has numerous advantages, a few of which are delineated, hereafter, as merely examples.
An advantage of the invention is that it improves test coverage in an integrated circuit.
An advantage of the invention is that it reduces the amount of time for testing an integrated circuit.
Another advantage of the invention is that it allows for continuously updating the test routine of an integrated circuit.
Another advantage of the invention is that it is simple in design and easily implemented on a mass scale for commercial production.
Another advantage of the invention is that it allows IC testing to be performed at the clock rate at which the IC was designed to operate.
Other features and advantages of the invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. These additional features and advantages are intended to be included herein within the scope of the present invention.